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LTC6903/LTC6904 1kHz - 68MHz Serial Port Programmable Oscillator
FEATURES
s s s s
DESCRIPTIO
s s s s s
s s s
1kHz to 68MHz Square Wave Output 0.5% (Typ) Initial Frequency Accuracy Frequency Error <1.1% Over All Settings 10ppm/C Typical Frequency Drift Over Temperature 0.1% Resolution 1.7mA Typical Supply Current (f < 1MHz, VS = 2.7V) 2.7V to 5.5V Single Supply Operation Jitter <0.4% Typical 1kHz to 8MHz Easy to Use SPI (LTC6903) or I2C (LTC6904) Serial Interface Output Enable Pin -40C to 125C Operation MS8 Package
The LTC(R)6903/LTC6904 are low power self contained digital frequency sources providing a precision frequency from 1kHz to 68MHz, set through a serial port. The LTC6903/LTC6904 require no external components other than a power supply bypass capacitor, and they operate over a single wide supply range of 2.7V to 5.5V. The LTC6903/LTC6904 feature a proprietary feedback loop that linearizes the relationship between digital control setting and frequency, resulting in a very simple frequency setting equation: 2078(Hz) f = 2OCT * ;1kHz < f < 68MHz DAC 2 - 1024 Where OCT is a 4-bit digital code and DAC is a 10-bit digital code. The LTC6903 is controlled by a convenient SPI compatible serial interface. The LTC6904 uses an industry standard I2C compatible interface.
, LTC and LT are registered trademarks of Linear Technology Corporation. U.S. Patent Numbers 6342817 and 6614313.
APPLICATIO S
s s s
s s
Precision Digitally Controlled Oscillator Power Management Direct Digital Frequency Synthesis (DDS) Replacement Replacement for DAC and VCO Switched Capacitor Filter Clock
TYPICAL APPLICATIO
A Microcontroller Controlling Its Clock
40 5V MICROCONTROLLER OSC1/CLKIN OSC2/CLKOUT MCLR/VP-P RC5/SDO RC3/SCK/SCL RC2/CCP1 GND SDI LTC6903 SCK SEN CLK 1F CLK 0.01F PIC16F73 POWER-UP CLOCK FREQUENCY IS 1039Hz 0 -1.0 10 V+ OE 10
VS = 3V TA = 25C f = 1039Hz 443 30 UNITS TESTED
10k
UNITS
20
5V 0.1F
VDD VSS VSS
6903 TA01
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LTC6903 Frequency Error Distribution
0 0.5 -0.5 FREQUENCY ERROR (%) 1.0
6903 TA01b
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LTC6903/LTC6904
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW GND SDI SCK SEN/ADR* 1 2 3 4 8 7 6 5 V+ OE CLK CLK
Total Supply Voltage (V+ to GND) .............................. 6V Maximum Voltage on any Pin ........................... (GND - 0.3V) VPIN (V+ + 0.3V) Output Short Circuit Duration (Note 2) ............ Indefinite Operating Temperature Range (Note 3) LTC6903CMS8/LTC6904CMS8 ........... -40C to 85C LTC6903IMS8/LTC6904IMS8 ............. -40C to 85C LTC6903HMS8/LTC6904HMS8 ......... -40C to 125C Specified Temperature Range (Note 4) LTC6903CMS8/LTC6904CMS8 ........... -40C to 85C LTC6903IMS8/LTC6904IMS8 ............. -40C to 85C LTC6903HMS8/LTC6904HMS8 ......... -40C to 125C Storage Temperature Range .................. -65C to 150C Lead Temperature (Soldering, 10sec)................... 300C
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150C, JA = 200C/W
LTC6903CMS8 LTC6903IMS8 LTC6903HMS8 LTC6904CMS8 LTC6904IMS8 LTC6904HMS8 MS8 PART MARKING*
* SEN (LTC6903) ADR (LTC6904)
LTABN LTAES
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V + = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL fi f PARAMETER Initial Frequency Accuracy Total Frequency Accuracy (Note 7) CONDITIONS f = 1.039kHz, V + = 3V, CLOAD = 5pF Single Output Active: Over All Settings, V + = 2.7V, CLOAD = 5pF Over All Settings, V + = 5.5V, CLOAD = 5pF LTC6903CMS8, LTC6904CMS8: Over All Settings, V + = 2.7V, CLOAD = 5pF Over All Settings, V + = 5.5V, CLOAD = 5pF LTC6903HMS8, LTC6903IMS8, LTC6904HMS8, LTC6904IMS8: Over All Settings, V + = 2.7V, CLOAD = 5pF Over All Settings, V + = 5.5V, CLOAD = 5pF MIN TYP MAX 0.75 0.5 0.5
q q
ELECTRICAL CHARACTERISTICS
UNITS % % % % %
1.1 1.6 1.65 2
0.5 0.5
q q
0.5 0.5 68 1.039 10 0.05 300 0.4 1
1.9 2.2
fMAX fMIN f/T f/V
Maximum Operating Frequency Minimum Operating Frequency Frequency Drift Over Temperature Frequency Drift Over Supply Long Term Frequency Stability Timing Jitter (See Graph) Duty Cycle 1.039kHz to 8.5MHz 1.039kHz to 68MHz 1.039kHz to 1MHz 1.039kHz to 68MHz CLK, CLK Pins, V + = 2.7V V + = 5.5V, 4mA Load V + = 2.7V, 4mA Load V + = 5.5V, 1mA Load V + = 2.7V, 1mA Load
q q q q q q q q q
ppm/C %/V ppm/kHr % % 51 % % V V V V 0.3 0.45 0.15 0.2 V V V V
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50 50 45 5.3 2.3 5.45 2.55 0.15 0.25 0.05 0.05
ROUT VOH
Output Resistance High Level Output Voltage
4.8 2 5.2 2.3
VOL
Low Level Output Voltage
V + = 5.5V, 4mA Load V + = 2.7V, 4mA Load V + = 5.5V, 1mA Load V + = 2.7V, 1mA Load
2
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% % MHz kHz
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WW
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LTC6903/LTC6904
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V + = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL tr tf PARAMETER Output Rise Time (10% - 90%) Output Fall Time (10% - 90%) CONDITIONS V + = 5.5V, RLOAD = , CLOAD = 5pF V + = 2.7V, RLOAD = , CLOAD = 5pF V + = 5.5V, RLOAD = , CLOAD = 5pF V + = 2.7V, RLOAD = , CLOAD = 5pF MIN TYP 1 1 1 1 MAX UNITS ns ns ns ns
ELECTRICAL CHARACTERISTICS
POWER REQUIRE E TS
SYMBOL VS IS, SHDN IS, DC PARAMETER Supply Voltage V+ Supply Current, Shutdown
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V + = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
CONDITIONS Applied Between V + and GND VS = 2.7V VS = 5.5V f = 68MHz, 5pF Load, V+ = 2.7V f < 1MHz, V+ = 2.7V f = 68MHz, 5pF Load, V+ = 5.5V f < 1MHz, V+ = 5.5V
q q q q q q q
V+ Supply Current, Single Output Enabled
SERIAL PORT ELECTRICAL CHARACTERISTICS+
SYMBOL VIH VIL IIN PARAMETER Min High Level Input Voltage SEN, SCK, SDI Pins Max Low Level Input Voltage SEN, SCK, SDI Pins Digital Input Leakage SEN, SCK, SDI Pins CONDITIONS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
MIN
q q q
TI I G CHARACTERISTICS +The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25C. V = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL PARAMETER LTC6903 (Notes 5, 6) fSCK tCKHI tCKLO tsu thLD tLCH tFCK Serial Port Clock Frequency Min Clock High Time Min Clock Low Time Min Setup Time - SDI to SCK Min Hold Time - SCK to SDI Min Latch Time - SEN to SEN Min First Clock - SEN to SCK
q q q q q q q q q q q q
LTC6904 (Notes 5, 6) fSMB SMBus Operating Frequency tBUF Bus Free Time Between Stop and Start Condition tHD, STA Hold Time After (Repeated) Start Condition tSU, STA Repeated Start Condition Setup Time tSU, STO Stop Condition Setup Time
UW
MIN 2.7
TYP 0.25 0.6 3.6 1.7 7 1.9
MAX 5.5 0.6 2.2 7 3.1 15 4.5
UNITS V mA mA mA mA mA mA
TYP
MAX 0.67 V+
UNITS V V
0.33 V+ 10
A
UW
MIN
TYP
MAX 20 25 25 10 10 400 20
UNITS MHz ns ns ns ns ns ns kHz s s s s
10 4.7 4.0 4.7 4.0
100
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LTC6903/LTC6904 TI I G CHARACTERISTICS +The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25C. V = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
PARAMETER
q q q q q q
SYMBOL
LTC6904 (Notes 5, 6) tHD, DAT Data Hold Time tSU, DAT Data Setup Time tLOW Clock Low Period tHIGH Clock High Period tf Clock, Data Fall Time tr Clock, Data Rise Time Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: A heatsink may be required to keep the junction temperature below the absolute maximum when the output is shorted indefinitely. Note 3: The LTC6903CMS8, LTC6904CMS8, LTC6903IMS8, and LTC6904IMS8 are guaranteed functional over the operating temperature range of -40C to 85C. The LTC6903HMS8 and LTC6904HMS8 are guaranteed functional over the extended operating temperature range of -40C to 125C. Note 4: The LTC6903CMS8 and LTC6904CMS8 are guaranteed to meet the specified performance limits over the 0C to 70C temperature range
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity
1.0 1.0
DIFFERENTIAL NONLINEARITY (LSB)
0.8
INTEGRAL NONLINEARITY (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 200 400 600 DAC SETTING 800 1000
6903 G01
FREQUENCY (%)
4
UW
UW
MIN 300 250 4.7 4.0
TYP
MAX
UNITS ns ns s s ns ns
50 300 1000
and are designed, characterized and expected to meet the specified performance from -40C to 85C but are not tested or QA sampled at these temperatures. The LTC6903IMS8 and LTC6904IMS8 are guaranteed to meet the specified performance limits over the -40C to 85C temperature range. The LTC6903HMS8 and LTC6904HMS8 are guaranteed to meet the specified performance limits over the -40C to 125C temperature range. Note 5: All values are referenced to VIH and VIL levels. Note 6: Guaranteed by design and not subject to test. Note 7: Parts with tighter frequency accuracy are available. Consult LTC Marketing for details.
Differential Nonlinearity
0.10 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 0 200 400 600 DAC SETTING 800 1000
6903 G01
Frequency vs Temperature
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
-0.10 -40 -20
0
20 40 60 80 TEMPERATURE (C)
100 120
6903 G03
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LTC6903/LTC6904 TYPICAL PERFOR A CE CHARACTERISTICS
Peak-to-Peak Jitter vs Frequency
10 V+ = 3V 10 9
PEAK-TO-PEAK JITTER (%)
7 6 5 4 3 2 1 V+ = 3V V+ = 5V
OUTPUT RESISTANCE ()
SUPPLY CURRENT (mA)
1
0.1
0.01 0.1
1 10 FREQUENCY (MHz)
Output Spectrum at 20MHz
20
0 0.5V/DIV 0.5V/DIV
10dB/DIV
-80 15MHz
20MHz
PI FU CTIO S
GND (Pin 1): Negative Power Supply (Ground). Should be tied directly to a ground plane for best performance. SDI ( Pin 2 ): Serial Data Input. Data for serial transfer is presented on this pin. SCK (Pin 3): Serial Port Clock. Input, positive edge triggered. Clocks serial data in on rising edge. SEN (Pin 4): Serial Port Enable (6903 Only). Input, active LOW. Initiates serial transaction when brought LOW, finalizes transaction when brought HIGH after 16 clocks. ADR (Pin 4): Serial Port Address (6904 Only). Sets the I2C serial port address. CLK (Pin 5): Auxiliary Clock Output. Frequency set by serial port. CLK (Pin 6): Main Clock Output. Frequency set by serial port. OE (Pin 7): Asynchronous Output Enable. CLK and CLK are set LOW when this pin is LOW. V+ (Pin 8): Positive Power Supply. This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a quality 0.1F capacitor. Additional bypass may be necessary for operation at high frequency or under larger loads.
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6903 G04 6903 G07
Supply Current vs Output Frequency
60 50 40 30 20 10
Output Resistance vs Supply Voltage
8
100
0 0.001
0.01
0.1 1 FREQUENCY (MHz)
10
100
6903 G05
0 2.5
3.0
3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.0
5.5
6903 G06
Output Waveform at 68MHz
Output Waveform at 20MHz
CL = 10pF V+ = 3V 25MHz
5ns/DIV
3468 G08
CL = 10pF V+ = 3V
10ns/DIV
3468 G09
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LTC6903/LTC6904
BLOCK DIAGRA W
V+ 8 OE 7 CLK 6 CLK 5
+ -
ISET
+
A1 MASTER OSCILLATOR fMO = 68MHz * k ISET V + - VSET OCT PROGRAMMABLE DIVIDER
-
VSET
DAC
SERIAL PORT 1 GND 2 SDI 3 SCK 4
6903 BD
SEN (LTC6903) ADR (LTC6904)
THEORY OF OPERATIO
The LTC6903/LTC6904 contain an internal feedback loop which controls a high frequency square wave VCO operating between 34MHz and 68MHz. The internal feedback loop frequency is set over an octave by a 10-bit resistor DAC. The VCO tracks the internal feedback loop frequency and the output frequency of the VCO is divided by one of sixteen possible powers of two. Higher VCO frequencies and lower output divider settings can result in higher output jitter. Random jitter at the lower
APPLICATIO S I FOR ATIO
Frequency Setting Information
The frequency output of the LTC6903/LTC6904 is determined by the following equation: f = 2OCT * 2078(Hz) DAC 2 - 1024
where DAC is the integer value from 0-1023 represented by the serial port register bits DAC[9:0] and OCT is the integer value from 0-15 represented by the serial port register bits OCT [3:0].
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frequency ranges is very low because of the high output divisor. The higher frequency settings will display some deterministic jitter from coupling between the control loop and the output. This shows up in the frequency spectrum as spurs separated from the fundamental frequency by 1MHz to 2MHz. Use the following two steps to choose binary numbers "OCT" and "DAC" in order to set frequency "f": 1) Use Table 1 to Choose "OCT" or use the following formula, rounding down to the integer value less than or equal to the result. f OCT = 3.322 log 1039 2) Choose "DAC" by the following formula, rounding DAC to the nearest integer:
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DAC = 2048 -
2078(Hz) * 2(10 + OCT) f
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APPLICATIO S I FOR ATIO
Table 1. Output Frequency Range vs OCT Setting (Frequency Resolution 0.001 * f)
f 34.05MHz 17.02MHz 8.511MHz 4.256MHz 2.128MHz 1.064MHz 532kHz 266kHz 133kHz 66.5kHz 33.25kHz 16.62kHz 8.312kHz 4.156kHz 2.078kHz 1.039kHz f< 68.03MHz 34.01MHz 17.01MHz 8.503MHz 4.252MHz 2.126MHz 1063kHz 531.4kHz 265.7kHz 132.9kHz 66.43kHz 33.22kHz 16.61kHz 8.304kHz 4.152kHz 2.076kHz
For example, to set a frequency of 6.5MHz, first look at Table 1 to find an OCT value. 6.5MHz falls between 4.25MHz and 8.5MHz yielding an OCT value of 12 or 1100. Substituting the OCT value of 12 and the desired frequency of 6.5MHz into the previous equation results in:
2078(Hz) * 2(10 +12) DAC = 2048 - = 707.113 6.5e6(Hz)
Rounding 707.113 to the nearest integer yields a DAC value of 707 (or a 10-bit digital word of 1011000011.) Power Up State When power is first applied to the LTC6903/LTC6904, all register values are automatically reset to 0. This results in an output frequency of 1.039kHz with both outputs active. Output Spectrum In most frequency ranges, the output of the LTC6903/ LTC6904 is generated as a division of the higher internal
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OCT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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clock frequency. This helps to minimize jitter and subharmonics at the output of the device. In the highest frequency ranges, the division ratio is reduced, which will result in greater cycle-to-cycle jitter as well as spurs at the internal sampling frequency. Because the internal control loop runs at 1MHz to 2MHz without regard to the output frequency, output spurs separated from the set frequency by 1MHz to 2MHz may be observed. These spurs are characteristically more than 30dB below the level of the set frequency. Frequency Settling When frequency settings change, the settling time and shape differ depending on which bits are changed. Changing only the OCT bits will result in an instantaneous change in frequency for OCT values below 10. Values of 10 and above may take up to 100s to settle due to the action of internal power conservation circuitry. Changing the DAC bits will result in a smooth transition between the frequencies, occupying at most 100s, with little overshoot. Changing both the OCT and DAC bits simultaneously may result in considerable excursion beyond the frequencies requested before settling. It should be noted that changing the DAC bits at the lower frequency ranges will result in a seemingly instantaneous frequency change because the settling time depends on the internal loop frequency rather than the set frequency. Power Supply Bypass In order to obtain the accuracies represented in this datasheet, it is necessary to provide excellent bypass on the power supply. Adequate bypass is a 1F capacitor in parallel with a 0.01F capacitor connected within a few millimeters of the power supply leads. Monotonicity and Linearity The DAC in the LTC6903/LTC6904 is guaranteed to be 10-bit monotonic. Nonlinearity of the DAC is less than 1%.
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LTC6903/LTC6904
APPLICATIO S I FOR ATIO
Additionally, the LTC6903/LTC6904 is guaranteed to be monotonic when switching between octaves with the OCT setting bits. For example, the frequency output with a DAC setting of "1111111111" and an OCT setting of "1100" will always be lower than the frequency output with a DAC setting of "0000000000" and an OCT setting of "1101". Linearity at these transition points is typically around 3 LSBs. Output Loading and Accuracy Improper loading of the outputs of the LTC6903/LTC6904, especially with poor power supply bypassing, will result in accuracy problems. At low frequencies, capacitive loading of the output is not a concern. At frequencies above 1MHz, attention should be paid to minimize the capacitive load on the CLK and CLK pins. The LTC6903/LTC6904 is designed to drive up to 5pF on each output with no degradation in accuracy. 5pF is equivalent to one to two HC series logic inputs. A standard 10x oscilloscope probe usually presents between 10pF and 15pF of capacitive load. It is strongly suggested that a high speed buffer is used when driving more than one or two logic inputs, when driving a line more than 5 centimeters in length, or a capacitive load greater than 5pF.
SEN
SCK
SDI
D15
D14
D13
D12
D11
D10
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Output Control The CLK and CLK outputs of the LTC6903/LTC6904 are individually controllable through the serial port as described in Table 2 below. The low power mode may also be accessed through these control bits. It is preferred that unused outputs be disabled in order to reduce power dissipation and improve accuracy. Disabling an unused output will improve accuracy of operation at frequencies above 1MHz. An unused output running with no load typically degrades frequency accuracy up to 0.2% at 68MHz. An unused output running into a 5pF load typically degrades frequency accuracy up to 0.5% at 68MHz.
Table 2. Output Configuration
CNF1 0 0 1 1 CNF0 0 1 0 1 CLK ON OFF ON CLK CLK + 180 ON OFF Powered-Down*
*Powered-Down: When in this mode, the chip is in a low power state and will require approximately 100s to recover. This is not the same effect as the OE pin, which is fast, but uses more power supply current.
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Serial Port Bitmap (LTC6903/LTC6904)
(All serial port register bits default LOW at power up)
Table 3
D15 OCT3 D7 DAC5 D14 OCT2 D6 DAC4 D13 OCT1 D5 DAC3 D12 OCT0 D4 DAC2 D11 DAC9 D3 DAC1 D10 DAC8 D2 DAC0 D9 DAC7 D1 CNF1 D8 DAC6 D0 CNF0
Timing Diagram (LTC6903)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
6903 TD01
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APPLICATIO S I FOR ATIO
Serial Port Register Description OCT[3:0] - Frequency Divider Setting. (See Frequency Setting Section) DAC[9:0] - Master Oscillator Frequency Setting. (See Frequency Setting Section) CNF[1:0] - Output Configuration - This controls outputs CLK and CLK according to Table 2. LTC6903 SPI Compatible Interface A serial data transfer is composed of sixteen (16) bits of data labeled D15 through D0. D15 is the first bit of data presented in each transaction. All serial port register bits are set LOW on power-up.
TI I G DIAGRA S
Timing Diagram (LTC6904)
SDA tSU, DAT tLOW SCL tHD, STA tr START CONDITION tHIGH tf REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tBUF tSU, STO
6903 TD02
Typical LTC6904 Input Waveform--Programming Frequency to 68MHz (ADR Pin Set LOW)
ADDRESS 0 START SDA 0 0 1 0 1 1 1 0 ACK 1 1 1 1 1 1 1 1 ACK 1 1 1 1 1 1 0 0 ACK 0 1 0 1 1 ADR WR OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0 STOP
SCL
1
2
3
4
5
6
7
8
9
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Writing Data (LTC6903 Only) When the SEN line is brought LOW, serial data presented on the SDI input is clocked in on the rising edges of SCK until SEN is brought HIGH. On every eighth rising edge of SCK, the preceding 8-bits of data are clocked into the internal register. It is therefore possible to clock in only the 8 {D15 - D8} most significant bits of data rather than completing an entire transfer. The serial data transfer starts with the most significant bit and ends with the least significant bit of the data, as shown in the timing diagram.
2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
6903 TD03
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LTC6903/LTC6904
TYPICAL APPLICATIO S
LTC6904 I2C Interface The LTC6904 communicates with a host (master) using the standard I2C 2-wire interface. The Timing Diagram shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus Accelerator, are required on these lines. If the I2C interface is not driven with a standard I2C compatible device, care must be taken to ensure that the SDA line is released during the ACK cycle to prevent bus contention. The LTC6904 is a receive-only (slave) device. The master can communicate with the LTC6904 using the Write Word protocols as explained later. The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another SMBus device. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. Write Word Protocol The master initiates communication with the LTC6904 with a START condition and a 7-bit address followed by the Write Bit (Wr) = 0. The LTC6904 acknowledges and the master delivers the most significant data byte. Again the LTC6904 acknowledges and the data is latched into the most significant data byte input register. The master then delivers the least significant data byte. The LTC6904 acknowledges once more and latches the data into the least significant data byte input register. Lastly, the master terminates the communication with a STOP condition. Slave Address The LTC6904 can respond to one of two 7-bit addresses. The first 6 bits (MSBs) have been factory programmed to 001011. The address pin, ADR (Pin 4) is programmed by the user and determines the LSB of the slave address, as shown in the table below:
ADR (Pin 4) 0 1 LTC6904 Address 0010111 0010110
1 S
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
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Write Word Protocol Used by the LTC6904
7 Slave Address 1 Wr 1 A 8 MS Data Byte 1 A 8 LS Data Byte 1 A 1 P
6903 AI01
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LTC6903/LTC6904
PACKAGE DESCRIPTIO
5.23 (.206) MIN
0.42 0.038 (.0165 .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT DETAIL "A" 0 - 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4)
0.254 (.010) GAUGE PLANE
0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.127 0.076 (.005 .003)
MSOP (MS8) 0204
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005) 3.20 - 3.45 (.126 - .136) 0.65 (.0256) BSC 3.00 0.102 (.118 .004) (NOTE 3) 8 7 65 0.52 (.0205) REF 0.53 0.152 (.021 .006) DETAIL "A" 1 1.10 (.043) MAX 23 4 0.86 (.034) REF 0.65 (.0256) BSC
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LTC6903/LTC6904
TYPICAL APPLICATIO
1 fCLK TRIG V+
Wide Range Time Interval Generator (1.97 Seconds to 4 Microseconds)
< TRIGGER PULSE WIDTH < OUTPUT PULSE WIDTH
+
C2 0.1F 1 GND V+ 8
SDI
2
SDI U6 LTC6903 SCK
OE
7
SCK
3
CLK
6 fCLK 5
SEN
4
SEN
CLK
S0 S1 S2 MUX SELECT ADDRESS LINES
RELATED PARTS
PART NUMBER LTC1799 LTC6900 LTC6902 DESCRIPTION 1kHz to 30MHz ThinSOTTM Oscillator 1kHz to 20MHz ThinSOT Oscillator Multiphase Oscillator with Spread Spectrum Modulation COMMENTS Single Output, Higher Frequency Operation Single Output, Lower Power 2, 3 or 4-Phase Outputs
69034fa
ThinSOT is a trademark of Linear Technology Corporation
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507 q www.linear.com
U
V 4 2 3 D PS U4 CLK R 1 Q Q 5 6 74HC74-A PHILIPS SEMICONDUCTOR C1 0.1F V+ 16 10 CLK Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 8 9 7 6 5 3 2 4 13 12 14 15 1 C3 0.1F V+ OUTPUT 2n PULSE = f CLK WIDTH Q Q 9 8 VOUT VOUT 16 4 3 2 1 15 14 13 12 11 10 9 7 D0 D1 D2 D3 D4 D5 D6 D7 S0 S1 S2 OE Y Y 6 5 QOUT 10 12 11 D PS U5 CLK R 13 V+ 74HC74-B PHILIPS SEMICONDUCTOR U1 11 MR 74HC4040 PHILIPS SEMICONDUCTOR 8 74HC251 PHILIPS SEMICONDUCTOR
6903 TA02
MUX Inputs
S2 0 1 0 1 0 1 0 1 S1 0 0 1 1 0 0 1 1 S0 0 0 0 0 1 1 1 1 n 4 5 6 7 8 9 10 11 Output Pulsewidth 16/fCLK 32/fCLK 64/fCLK 128/fCLK 256/fCLK 512/fCLK 1024/fCLK 2048/fCLK
LT/TP 0404 1K REV A * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2003

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